This invention relates to semiconductor memory devices and method of manufacture, and more particularly to an electrically erasable, programmable read only memory of the floating gate type.
Nonvolatile memory devices using a floating gate to retain charge are made by a double level polysilicon process as set forth in U.S. Pat. No. 4,122,544 issued to David J. McElroy and U.S. Pat. No. 4,112,509 issued to Lawrence S. Wall, both assigned to Texas Instruments, or in U.S. Pat. No. 3,984,822 issued to Simko et al. These devices are widely used in microcomputers, particularly in program development.
The device of the McElroy patent included a series enhancement transistor designed to correct the problem of over-erasure wherein the channel beneath the floating gate went into depletion mode so the memory transistor would conduct even with zero volts on the control gate. However, to avoid a read-disturb condition and an over-erase phenomena, and improve speed, cell designs with an erase window were developed, as disclosed in pending applications Ser. No. 1,095 (now U.S. Pat. No. 4,267,558, issued May 12, 1981), and Ser. No. 1,097 (now U.S. Pat. No. 4,302,766, issued Nov. 24, 1981), filed Jan. 5, 1979, by Guterman and Chin, assigned to Texas Instruments.
The cell size in these prior floating gate electrically erasable EPROMs has been large due to the cell layout and configuration, and other features necessary because of the process used for manufacture. Smaller cell size is desirable in order to provide a more dense array with more cells in a given silicon area, and/or to lower cost and increase yields in manufacture.
It is the principal object of this invention to provide an improved electrically erasable, programmable memory. Another object is to provide an electrically erasable EPROM of reduced cell size. An additional object is to provide a dense array of electrically erasable EPROM cells, made by a more efficient method.